1. Field of the Invention
This invention relates generally to a processing circuit for use with a central processing unit (CPU), and particularly to a processor including an error detecting and correcting circuit.
2. Prior Art
Referring to FIG. 3, the conventional processor system generally comprises a data input portion 209, an error detecting and correcting circuit 208, an output bus 206, a register 207, a first input data latch 204 and a second input data latch 205, an arithmetic unit 201, a first input bus 202, and a second input bus 203.
The operation of the conventional processor system having the above-mentioned structure will be described hereinbelow. When data is inputted, the data and an error detecting and correcting code are inputted into the error detecting and correcting circuit 208 from the data input portion 209. In the error detecting and correcting circuit 208, whether the data is correct or not is checked. If the data is not correct, the data is corrected, and such corrected data is inputted into the register 207 via the output bus 206. When the corrected data is subsequently used in the arithemetic unit 201, the inputted data in the register 207 is read out therefrom at the next cycle step. Then, the data is sent to the arithmetic unit 201 via the first input data latch 204 and the first input bus 202 or via the second input data latch 205 and the second input bus 203. In the arithmetic unit 201, an operation is performed by using such sent data.
FIG. 4 is a timing chart of the operation of the conventional processor system. In a step 0, data is inputted into the data input portion 209. In a step 1, the data is written in the register 207 after the error detection and correction of the data is performed. In a step 2, the written data is read out and latched in the first input data latch 204 or second input data latch 205. Then, the operation is started from a step 3.
However, in such a conventional processor system, the speed of a data reading operation is made low, thereby decreasing the execution speed of a program because the data reading operation is performed so many times on the execution of program steps.